Xilinx ISE - Getting ports outside on the IO Block

[firozjdang]

I am working on an Design IP implemented on an FPGA, and to debug the outputs or inputs I have to add more ports to the module or also get some register or wire outputs on the IO ports for debug. But changing every time the modules(go through 5-6 hierarchy ) and again synthesizing the design and then Implementing it is very time consuming and stressful. Is any one aware of any tool in Xilinx ISE PlanAhead or FPGA Editor can actually get the present register or wires out on particular desired IO port? So that I synthesize the design once and to check the inside signal's behaviour I get these signals out on the IO port to debug????

 

[guitarguy12387]

If i were you, I'd use chipscope.

 

[blooz]

Using chipscope Will be a good idea ,you can monitor many signals simultaneously

 

[firozjdang]

Well, I am not using JTAG to access the FPGA, I am using USB micro controller, that is the issue, It does have JTAG pins on the connector board but my project is being implemented and controlled entirely by software application....

 

[mrflibble]

What's stopping you from using that jtag port for chipscope debugging?