It is used for passing along IP cores. For example, if Xilinx make a PCI core, they may not want to give the source, but using coregen, the IP is pre-synthesized and generated as an EDIF file targetted/optimized for your specific FPGA (Spartan 3, Virtex 2, ...), along with wrapper VHDL or Verilog code.
I would say that Xilinx make their best to make the implementation as optimized as possible for their FPGA fabric.
You can always hand-write your own cores. Use CoreGen if you wish to use Xilinx IP cores.
Note that CoreGen is not the same as the architecture wizard. The architecture wizard will create simpler constructs, along with full source code. The architecture wizard is used simply to simplify instantiation of Xilinx constructs (where coregen is used to instantiate full-sized complex cores). For example, when using the DCM, this give you a step by step wizard, and generate source code along.
Big Boy