Xilinx ISE Coregenerator...is it really usefull?

[vahidkh6222]

i am not sure about ISE COREgenerator.... can we say that this is like other compiler that are not as optimised as manual coding?!!
my question is : is the final result of these automatic coregeneratore, more optimised than self-written VHDL code? or it is just another wizzard that just simplify some simple things?!!

 

[vahidkh6222]

i mean is it an instantiation of some macrocells inside of FPGA or, just a automatic generated codes?

 

[Big Boy]

It is used for passing along IP cores. For example, if Xilinx make a PCI core, they may not want to give the source, but using coregen, the IP is pre-synthesized and generated as an EDIF file targetted/optimized for your specific FPGA (Spartan 3, Virtex 2, ...), along with wrapper VHDL or Verilog code.

I would say that Xilinx make their best to make the implementation as optimized as possible for their FPGA fabric.

You can always hand-write your own cores. Use CoreGen if you wish to use Xilinx IP cores.

Note that CoreGen is not the same as the architecture wizard. The architecture wizard will create simpler constructs, along with full source code. The architecture wizard is used simply to simplify instantiation of Xilinx constructs (where coregen is used to instantiate full-sized complex cores). For example, when using the DCM, this give you a step by step wizard, and generate source code along.

Big Boy

 

[Blowfishie]

Take the case of writing a FIFO.

You can write your own, for sure, but why bother when the Coregen wizard just asks you for the FIFO's design parameters and creates something that works right away.

You may be able to make a more optimised design. You can directly instantiate primitives in your code and hand-place/route in the FPGA editor. If you do, you are aiming to push every last Hz of performance out of the FPGA.

Is that what you intend or is time to market more important than getting lots of one-on-one time with the FPGA fabric?

 

[xugefu]

In my experience, when I want to implement a larger memory block, I have to use IP core so that I can use the flash memory on the FPGA board (PCB) . Otherwise, FPGA will systhesize my memory block using FFs and that will exhaust all useable FFs inside FPGA.

 

[JaneZhong]

In my opinion, self-written VHDL code is more flexible. But if you need to design a universal and complex module, you can make use of the coregenerator to help your design because of the optimised design by xilinx