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Xilinx Inc. has added advanced physical
synthesis, support for formal verification and other high-end
technologies heretofore used in ASIC design to a major
revision of its Integrated Software Environment FPGA design
FPGAs are encroaching on ASIC turf, with the latest devices
hitting 6 million system gates and running at speeds of 300
to 400 MHz, said Rich Sevcik, senior vice president and
general manager of the FPGA products group at Xilinx. This
is enticing ASIC designers to move to the more forgiving,
albeit more expensive, FPGAs, Sevcik said.
Thus, Integrated Software Environment (ISE) 4.1i not only
has a run-time improvement, as in past upgrades, but also
new features and support for tools familiar to ASIC
designers, such as formal verification. "We really play in the
heart of the ASIC market, and we have been picking up
7,000 new design engineers a quarter for the last six
quarters," said Sevcik.
To accommodate ASIC designers' move into FPGA design,
Sevcik said that Xilinx has given the ISE 4.1i links to formal
verification tools from Synopsys Inc. and Verplex Systems Inc. as well as Synopsys'
PrimeTime static timing tool. "We've been working with companies like MTI [Model
Technology], Synopsys and Verplex for about a year and a half to integrate these
tools in our flow," said Sevcik. "This allows ASIC designers to use the tools they are
familiar with and do the verification runs they like to do."
Xilinx further worked with Synopsys to link that company's Leda HDL
source-checking software to the latest version of ISE.