Xilinx ISE 12.3 : library simprim not found

Hi, I'm using ISE 12.3 to implement a design.
I generate a verilog netlist which contains cells of the simprim library.
Then I take this netlist and do some changes on it ( split it in parts for example ). But if I start a new project whith the new files, ise can't find simprims library.
Can anyone explain me what to do?
thx

Compile the libraries from inside ISE.

I used this command line :
netgen -w -ecn conformal -ne -mhf clockbuf

I obtained 2 verilog files : glbl.v & clockbuf_ecn.v
I start a new project with these 2 files, and i include all verilog files of used cells from the simprim library. and here is what I obtain :

ERROR:HDLCompilers:244 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_OBUF.v" line 36 Name 'glbl.GTS' could not be resolved
ERROR:HDLCompilers:185 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_OBUF.v" line 36 Illegal right hand side of continuous assign
ERROR:HDLCompilers:244 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 42 Name 'glbl.GSR' could not be resolved
ERROR:HDLCompilers:185 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 42 Illegal right hand side of continuous assign
ERROR:HDLCompilers:244 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_BUFGMUX.v" line 46 Name 'glbl.GSR' could not be resolved
ERROR:HDLCompilers:185 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_BUFGMUX.v" line 46 Illegal right hand side of continuous assign

Thanks for your help.

Just run the command "compxlib" and it will compile your libraries for you.

first add
<ISE>\verilog\src\glbl.v
into ur project and then try :
netgen -w -ecn conformal -ne -mhf clockbuf glbl

Hi all, I'm not sure that I asked the best question. Here it is : If I implement any design with ISE, then I use netgen to generate a new verilog netlist (lets call it newNet.v), can I take "newNet.v" and start a new project with it or not?
I do not want to run simulation but I want to implement "newNet.v" and synthesize it with XST.
The problem now is that "newNet.v" uses SIMPRIM files and "glbl.v" when I use these options with netgen :
netgen -w -ecn conformal -ne -mhf clockbuf

I looked in the code provided by xilinx, and i found that it is instantiated as follows :
tri0 GSR = glbl.GSR; // in X_FF.v for example

And the errors are like this :
ERROR:HDLCompilers:244 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 42 Name 'glbl.GSR' could not be resolved
ERROR:HDLCompilers:185 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 42 Illegal right hand side of continuous assign

I read in xilinx forum that glbl is only used for simulation !!! That why I want tu use another library for synthesis.
Any ideas? Thx again for your help.

I think I've got it I have generated 4 models
1) Post-Synthesis Simulation model
2) Post-Translate Simulation model
3) Post-Map Simulation model
4) Post-Place & Route Simulation model

1 uses UNISIM cells. If I start a new project with it, ISE recognises all the cells and synthesize the design and it's OK !!!
2, 3 and 4 use SIMPRIMS cells. If I start a new project with one of these, ISE needs the verilog files of used cells (X_FF for example). If I include files from ~/ISE/ISE_DS/ISE/verilog/src/simprims/ , then I have the problem of glbl.
I tried also to include cells of SIMPRIMS from ~/ISE/ISE_DS/ISE/verilog/xeclib/simprims because they do not use glbl.v but now I have another primitive include problem !!!