xman52
Newbie level 4
xilinx lit:244
Hello
Please go through this report . This is the Design overwie summary of my project and it has REMOVED BLOCK SECTION 5 . Can anyone help me how to avoid this! Or what is the problem in my code?! How to avoid tis optimization.
this is the report....
Release 10.1 Map K.31 (nt)
Xilinx Mapping Report File for Design 'datapath'
Design Information
------------------
Command Line : map -ise "D:/student/shk/edited single/new_power/new_power.ise"
-intstyle ise -p xc3s500e-pq208-5 -cm area -pr off -k 4 -c 100 -o
datapath_map.ncd datapath.ngd datapath.pcf
Target Device : xc3s500e
Target Package : pq208
Target Speed : -5
Mapper Version : spartan3e -- $Revision: 1.46 $
Mapped Date : Wed Jul 22 22:20:41 2009
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 2,438 out of 9,312 26%
Number of 4 input LUTs: 2,344 out of 9,312 25%
Logic Distribution:
Number of occupied Slices: 2,307 out of 4,656 49%
Number of Slices containing only related logic: 2,307 out of 2,307 100%
Number of Slices containing unrelated logic: 0 out of 2,307 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 2,406 out of 9,312 25%
Number used as logic: 2,344
Number used as a route-thru: 62
Number of bonded IOBs: 66 out of 158 41%
Number of BUFGMUXs: 1 out of 24 4%
Peak Memory Usage: 168 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 6 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+----------------------------------------------------------------------------------------------------------------------------------------+
| clk | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| i_rst | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<0> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<1> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<2> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<3> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<4> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<5> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<6> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<7> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<8> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<9> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<10> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<11> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<12> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<13> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<14> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<15> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<16> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<17> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<18> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<19> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<20> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<21> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<22> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<23> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<24> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<25> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<26> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<27> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<28> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<29> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<30> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<31> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| r_out_A<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<16> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<17> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<18> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<19> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<20> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<21> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<22> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<23> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<24> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<25> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<26> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<27> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<28> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<29> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<30> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<31> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
+----------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
Section 11 - Timing Report
--------------------------
This design was not run using timing mode.
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 14 - Utilization by Hierarchy
-------------------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM | MULT18X18 | BUFG | DCM | Full Hierarchical |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
| datapath/ | | 63/2371 | 0/2438 | 64/2406 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | datapath |
| +al | | 200/200 | 112/112 | 340/340 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | datapath/al |
| +d | | 832/832 | 1065/1065 | 648/648 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | datapath/d |
| +i | | 187/187 | 98/98 | 281/281 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | datapath/i |
| +r | | 1089/1089 | 1163/1163 | 1073/1073 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | datapath/r |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Slices can be packed with basic elements from multiple hierarchies.
Therefore, a slice will be counted in every hierarchical module
that each of its packed basic elements belong to.
** For each column, there are two numbers reported <A>/.
<A> is the number of elements that belong to that specific hierarchical module.
is the total number of elements from that hierarchical module and any lower level
hierarchical modules below.
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
Please help me! How to get rid of the optimization done by removing two blocks of my design..this is needed for me while analysing power!!??
Please help...
Hello
Please go through this report . This is the Design overwie summary of my project and it has REMOVED BLOCK SECTION 5 . Can anyone help me how to avoid this! Or what is the problem in my code?! How to avoid tis optimization.
this is the report....
Release 10.1 Map K.31 (nt)
Xilinx Mapping Report File for Design 'datapath'
Design Information
------------------
Command Line : map -ise "D:/student/shk/edited single/new_power/new_power.ise"
-intstyle ise -p xc3s500e-pq208-5 -cm area -pr off -k 4 -c 100 -o
datapath_map.ncd datapath.ngd datapath.pcf
Target Device : xc3s500e
Target Package : pq208
Target Speed : -5
Mapper Version : spartan3e -- $Revision: 1.46 $
Mapped Date : Wed Jul 22 22:20:41 2009
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 2,438 out of 9,312 26%
Number of 4 input LUTs: 2,344 out of 9,312 25%
Logic Distribution:
Number of occupied Slices: 2,307 out of 4,656 49%
Number of Slices containing only related logic: 2,307 out of 2,307 100%
Number of Slices containing unrelated logic: 0 out of 2,307 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 2,406 out of 9,312 25%
Number used as logic: 2,344
Number used as a route-thru: 62
Number of bonded IOBs: 66 out of 158 41%
Number of BUFGMUXs: 1 out of 24 4%
Peak Memory Usage: 168 MB
Total REAL time to MAP completion: 7 secs
Total CPU time to MAP completion: 6 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+----------------------------------------------------------------------------------------------------------------------------------------+
| clk | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| i_rst | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<0> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<1> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<2> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<3> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<4> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<5> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<6> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<7> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<8> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<9> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<10> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<11> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<12> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<13> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<14> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<15> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<16> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<17> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<18> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<19> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<20> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<21> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<22> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<23> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<24> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<25> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<26> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<27> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<28> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<29> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<30> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| pc_in<31> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| r_out_A<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<16> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<17> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<18> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<19> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<20> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<21> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<22> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<23> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<24> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<25> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<26> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<27> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<28> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<29> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<30> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| r_out_A<31> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
+----------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
Section 11 - Timing Report
--------------------------
This design was not run using timing mode.
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 14 - Utilization by Hierarchy
-------------------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM | MULT18X18 | BUFG | DCM | Full Hierarchical |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
| datapath/ | | 63/2371 | 0/2438 | 64/2406 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | datapath |
| +al | | 200/200 | 112/112 | 340/340 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | datapath/al |
| +d | | 832/832 | 1065/1065 | 648/648 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | datapath/d |
| +i | | 187/187 | 98/98 | 281/281 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | datapath/i |
| +r | | 1089/1089 | 1163/1163 | 1073/1073 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | datapath/r |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Slices can be packed with basic elements from multiple hierarchies.
Therefore, a slice will be counted in every hierarchical module
that each of its packed basic elements belong to.
** For each column, there are two numbers reported <A>/.
<A> is the number of elements that belong to that specific hierarchical module.
is the total number of elements from that hierarchical module and any lower level
hierarchical modules below.
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
Please help me! How to get rid of the optimization done by removing two blocks of my design..this is needed for me while analysing power!!??
Please help...
