xilinx IO logic and timing constraints

[buenos]

Hi

I have generated a high-speed AD converter interface in Xilinx Coregenerator for a Spartan-6 device. 400MT/s DDR with LVDS signalling. It uses IBUFDS, IBUFGDS, IDDR2 and BUFIO2 primitives.

My problem is that the Coregenerator did not create any timing constraints. I am trying to set up some timing constraints in my project's main UCF file:

NET "ADC_CLK_IN_P" TNM_NET = "ADC_CLK_IN";
TIMESPEC TS_ADC_CLK_IN = PERIOD "ADC_CLK_IN" 5 ns HIGH 50 %;

INST "ADC_DATA_IN_P<0>" TNM = "ADC_DATA";
INST "ADC_DATA_IN_P<1>" TNM = "ADC_DATA";
INST "ADC_DATA_IN_P<2>" TNM = "ADC_DATA";
INST "ADC_DATA_IN_P<3>" TNM = "ADC_DATA";
INST "ADC_DATA_IN_P<4>" TNM = "ADC_DATA";
INST "ADC_DATA_IN_N<0>" TNM = "ADC_DATA";
INST "ADC_DATA_IN_N<1>" TNM = "ADC_DATA";
INST "ADC_DATA_IN_N<2>" TNM = "ADC_DATA";
INST "ADC_DATA_IN_N<3>" TNM = "ADC_DATA";
INST "ADC_DATA_IN_N<4>" TNM = "ADC_DATA";

#the constraints: (max t_xx)
# input setup:
TIMEGRP "ADC_DATA" OFFSET = IN 1 ns BEFORE "ADC_CLK_IN";
# input hold:
#TIMEGRP "ADC_DATA" OFFSET = IN 1 ns AFTER "ADC_CLK_IN";

is this any close to be correct?
what else do i need to setup?

regards,
buenos