I'm design one project in vhdl/verilog, now i am stuck with to calculate the area.
with the help of formula we can able to find? what formula ?
what values we have to use ?
You guys can help me to finding the area in Xilinx.
This is very open-ended. Its not hard to fill any FPGA with a solution to a hard problem. Therefore I expect 100% area use of the largest current FPGA.
Perhaps you have a more specific problem with more specific latency/BW requirements.
You have to synthesize the project in xilinx ise and you will get a report from the fitter about the area occupied in the specified cpld/fpga.
Fitting can only be done using the chips vendor tools, there is no formula to calculate it.