mr.jonam
Newbie level 1
I am using Xilinx dev. board (Spartan-6 LX45T FPGA based SP605), running MicroBlaze processor with AXI GPIO module to drive a external board. Facing a timing issue with this design.
Can someone suggest how to use GPIO as a separate IP-Core (not xilinx EDK default) and share some register to communicate between MicroBlaze and the GPIO. Essentially i need suggestion on following two technique.
1. Design the VHDL to implement GPIO available in said board (SP605).
2. Communicate between MicroBlaze and thie custom IP core for GPIO.
Please suggest me.
Can someone suggest how to use GPIO as a separate IP-Core (not xilinx EDK default) and share some register to communicate between MicroBlaze and the GPIO. Essentially i need suggestion on following two technique.
1. Design the VHDL to implement GPIO available in said board (SP605).
2. Communicate between MicroBlaze and thie custom IP core for GPIO.
Please suggest me.