Xilinx FPGA's tap delays and MIG design calibration.

[syedshan]

Hello everyone,

every one, I have a problem doing read calibration (both calibration level 1 and level 2) and I was looking for possible causes. Among few others I found one related to tap delays and since I am listing out one by one, the tap delay thing remains obscure to me. seeing several posts and xilinx forums I have an idea it has something to do with setting these values...

But what exactly are they?

Jaffry

 

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The tap delays are for the IODELAY cell, it sets the amount of delay inserted for the pin. The added delay per tap is defined by a nominal 200 MHz clock that is connected to the IODELAYCTRL, it's something like (1/200e6)/128 or maybe by 256 don't exactly remember.

The MIG tool generates some calibration code that outputs bit patterns on the memory interface and reads them back as it sweeps the IODELAY values across the entire range. Once it finds the center of the eye it sets the delay on that I/O to center the data eye in the middle of the read clock.