FlyingDutch
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Hello,
has anybody experience with this cheap board based on Spartan6 (XC6SLX25) from AliExpress.com - here is link to it:
https://www.aliexpress.com/item/400...lo2pol&spm=a2g0o.cart.0.0.48433c00KH9Scy&mp=1
I would like to try project with vintage "Nintendo NES" game console. Here is "Github" repository with code for this project:
https://github.com/Saanlima/Pepino/tree/master/Projects/Pepino_NES_smb
I tried to synthesis this code and it takes many of FPGA resourcers (LUTs ,FF, Block-RAM) - the smallest FPGA chip meets this number of resources is Spartan6 XC6SLX25. Project is in "Xilinx ISE" and contains many of "ISE IP-Cores" so I wouldn't try to implement it on Xilinx 7 series FPGAs (Spartan7 or Artix7) which is required "Xilinx Viavado". Any comments related to mentioned board will be warmly Welcome. Especially I be grateful for schematics and "User constraint" file example for ISE.
Best regards
has anybody experience with this cheap board based on Spartan6 (XC6SLX25) from AliExpress.com - here is link to it:
https://www.aliexpress.com/item/400...lo2pol&spm=a2g0o.cart.0.0.48433c00KH9Scy&mp=1
I would like to try project with vintage "Nintendo NES" game console. Here is "Github" repository with code for this project:
https://github.com/Saanlima/Pepino/tree/master/Projects/Pepino_NES_smb
I tried to synthesis this code and it takes many of FPGA resourcers (LUTs ,FF, Block-RAM) - the smallest FPGA chip meets this number of resources is Spartan6 XC6SLX25. Project is in "Xilinx ISE" and contains many of "ISE IP-Cores" so I wouldn't try to implement it on Xilinx 7 series FPGAs (Spartan7 or Artix7) which is required "Xilinx Viavado". Any comments related to mentioned board will be warmly Welcome. Especially I be grateful for schematics and "User constraint" file example for ISE.
Best regards
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