Dear Rberek
Many many thanks for having rescued me!
The short test and the final application (1100 lines of vhdl code) worked fine immediately. Easier than I can say once understood.
And yes ISE knows how much BRAM to take. It does use the expected 8 blocks.
Wonderful tool.
Congratulations for your guidance - from a 75 years old university Physics prof moderately experienced with FPGA's and VHDL, but with 40 years of scientific computing in more than 25 languages including at least 10 assemblers...
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Thanks again.
I begin to understand and as I progress I do find the documentation, unfortunately spread in many places - not easy for somebody who sees that for the first time...
May I ask one hopefully last question?
I configured the core for a BRAM buffer of width 36 and depth 4096 .
The ISE Device Utilisation Summary reports under Number of RAMB 16BWEs :
Used 1, available 20, Utilization 5%.
The utilization figure matches my Spartan 3AN FPGA which indeed has 360kbits of BRAM since one block has 18 kbits (incl. 2 for parity).
But I expected my buffer definition to need 8 such blocks, not 1.
Could it be that the ISE software is clever enough to find that although I requested
144kbits my actual code for this training test uses only 288 bits, thus needs no more than one RAMB-16BWE ?
Or should I suspect a bad generation of the core?
Best regards
Yanqele