Long time since last login.
I have to say the data flow from CIC to HB ,then to FIR have been such a nightmare for me.
i use the CIC .HB and FIR filter in my project of DDC.
the sampling data go through mixer,the to the three filter above.
the word length to cic is 20bits, output data is 20 bits also. that is to say i use 20 bit as the bus length between the connection of the three filter.
just as the symbol above ,the first is cic filter make a rate of 40 decimation
then hb filter decimate as a rate of 8, then the pfir filter to shape the spectrum.and they are working under the same clock :32.768MHZ.
the data frequency and clock frequency of cic_40 is 32.768MHZ, the HB_8filter receive the data from cic, that is to say the input data frequency is 32.768M/40=819.2k,output data frequency is 102.4hz, the clock of this module is 32.768M,we have mentioned it just now.
the last stage is fir filter.input data is from hb filter .data frequency is 102.4khz and so is the output data frequency.
1 how to resolve the problem of bit growth. and make a truncation 2 how to use handshake signal . i 'm sorry not to understand what you try to say last time.
I'm lookint forward for your reply. and anyone who can give me construction.
MANYTHANKS
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the pict of cic simulation
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This is the signal of three filter
Code:
module cic40 (
rfd, rdy, nd, clk, dout, din
);
output rfd;
output rdy;
input nd;
input clk;
output [19 : 0] dout;
input [19 : 0] din;
Code:
module hb8 (
rfd, rdy, nd, clk, dout, din
);
output rfd;
output rdy;
input nd;
input clk;
output [19 : 0] dout;
input [19 : 0] din;
Code:
module pfir (
rfd, rdy, nd, clk, dout, din
);
output rfd;
output rdy;
input nd;
input clk;
output [19 : 0] dout;
input [19 : 0] din;
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hb filter behavioral
simulation
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fir filter behavioral simulation