xilinx fifo depth and reading 00's

[electronrancher]

Hi,

Might be a dumb question, but I'd appreciate a serious answer nonetheless. I built a fifo in coregen (FWFT) of depth 16 and latched 1 word of data to it. I found that I had to read out 00's 15 times before I saw my data word. This seems... wrong. Is it? I was expecting to get my first word on the first read, not have to shift through a bunch of garbage before I got my data.

 

[rberek]

This is not expected behaviour. You would expect to see the data in the first address appear on the output port soon after being stored. The action of reading the data increments the FIFO read address.

Without seeing code or waveforms it is hard to say exactly what is the cause of the problem.

r.b.

 

[barry]

That's not a fifo, that's a shift register.

 

[electronrancher]

Yeah no kidding. Thanks guys for the sanity check, I bet the problem is wr_en going high initially and stuffing empty data. The debug was made more difficult because even in version 9.2, the default behavioral models just don't act right. You'd think they'd be able to get it accurate after 9 major releases and who knows how many updates. But structural model seems to be working right.

 

[rberek]

There were some issues in the behavioural models earlier on, but I thought they were fixed. If the 9.2 you are referring to is the version of ISE, then you should update to the latest version, which is 14.7.

r.b.

 

[mrflibble]

Indeed. That and other assorted other weirdness more or less settled around version 11. I was also thinking "why the hell punish yourself with 9.2?", but you're probably stuck with it due to this being an old project or some such? Because if this is not an old project ==> use something from the 14.x range.