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| `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/07/2018 10:11:10 PM
// Design Name:
// Module Name: datain
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
module datain(
);
parameter CLOCK_PERIOD=100;
parameter width=10;
parameter frameSize=400;
reg clk,reset,val;
reg [0:2*width-1] windowOut;
reg donewin;
reg last;
reg [19:0] m_axis_data_tdata_re;
reg [19:0] m_axis_data_tdata_im;
wire s_axis_config_tready;
reg [19:0]povey[0:399];
reg [7:0] s_axis_config_tdata;
wire s_axis_data_tready;
integer i;
wire m_axis_data_tready ;
wire event_frame_started;
wire event_tlast_unexpected;
wire event_tlast_missing;
wire event_status_channel_halt;
wire event_data_in_channel_halt ;
wire event_data_out_channel_halt;
wire m_axis_data_tvalid;
wire [47:0] m_axis_data_tdata;
wire m_axis_data_tlast;
integer file;
integer file1;
integer file3;
integer stat;
initial
begin
i=0;
clk=0;
reset=0;
donewin =0;
last =0;
windowOut = 20'b0; //20=2*width
file3= $fopen("in.mem","r");
while (! $feof(file3))
begin
stat=$fscanf(file3,"%d",povey[i]);
i=i+1;
end
$fclose(file3);
#10 i=0;
#20 reset<=1;
#80 reset <=0;
val<=1;
s_axis_config_tdata <=8'b0;
file= $fopen("outre.txt","w");
file1= $fopen("outim.txt","w");
end
always @(posedge clk)
begin
if(val)
begin
windowOut<=povey[i];
i<=i+1;
donewin<=1;
last <=0;
end
end
always @(posedge clk)
begin
if((i>399) && (i <512))
begin
windowOut<=0;
i<=i+1;
donewin<=1;
last<=0;
val<=0;
end
if(i==511)
begin
i <=0;
last <=1;
end
if(last==1) donewin<=0;
end
xfft_0 uut (
.aclk(clk),
.aresetn(~reset),
.s_axis_config_tvalid(donewin),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_config_tdata(s_axis_config_tdata),
.s_axis_data_tvalid(donewin),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tdata(windowOut),
.s_axis_data_tlast(last),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(m_axis_data_tlast),
.event_frame_started(event_frame_started),
.event_tlast_unexpected(event_tlast_unexpected),
.event_tlast_missing(event_tlast_missing),
.event_status_channel_halt(event_status_channel_halt),
.event_data_in_channel_halt(event_data_in_channel_halt),
.event_data_out_channel_halt(event_data_out_channel_halt)
);
always @(posedge clk)
begin
if(m_axis_data_tvalid==1)
begin
m_axis_data_tdata_re <= m_axis_data_tdata[19:0];
$fwrite(file,m_axis_data_tdata[19:0]);
m_axis_data_tdata_im <= m_axis_data_tdata[43:24];
$fwrite(file,m_axis_data_tdata[43:24]);
end
end
always #(CLOCK_PERIOD/2) clk <= ~clk;
endmodule |