moving2
Junior Member level 1
- Joined
- Jul 10, 2013
- Messages
- 19
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1
- Activity points
- 168
I am attempting to perform a post-route simulation on a design containing a Xilinx DCM on a Virtex-II Pro used in Variable Phase Shift mode.
In behavioral simulation, when the DCM first locks and no phase shift is applied, the reference clock (clkin) and the clk0 (clkfb) of the DCM are in phase.
However, in the post-route simulation, when the DCM first locks and no phase shift is applied, the reference clock and the clk0 (clkfb) of the DCM are not at all in-phase.
I am resetting the DCM and applying phase shift exactly according to the spec sheet and Xilinx App Notes. Is this a known limitation of the Xilinx post-route DCM model, or does this reflect actual behavior? If it does reflect actual behavior, then how do I start the design with 0 phase shift between the reference clk (clkin) and clk0/clkfb?
Thanks in advance for any help you can provide.
In behavioral simulation, when the DCM first locks and no phase shift is applied, the reference clock (clkin) and the clk0 (clkfb) of the DCM are in phase.
However, in the post-route simulation, when the DCM first locks and no phase shift is applied, the reference clock and the clk0 (clkfb) of the DCM are not at all in-phase.
I am resetting the DCM and applying phase shift exactly according to the spec sheet and Xilinx App Notes. Is this a known limitation of the Xilinx post-route DCM model, or does this reflect actual behavior? If it does reflect actual behavior, then how do I start the design with 0 phase shift between the reference clk (clkin) and clk0/clkfb?
Thanks in advance for any help you can provide.