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xilinx core gen generate comparator v8_0 meet problem

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Matrix_YL

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problem encountered processing rpms.

Hi all

I use core gen to generate comparator v8.0 core and add comparator_v8_0.vhd to project. then Implement Design directly
but meet error
Code:
ERROR:Map:116 - The design is empty.  No processing will be done.
ERROR:Map:52 - Problem encountered processing RPMs. 
ERROR: MAP failed
my project just has a comparator v8.0 core ,it can be sysnthesizd !what wrong with it ? whether the core can be used directly without instance it in HDL(I means it need to instantiate in another module ) if not what shall I do ?
thx in advance
 

echo47

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www.edaboard.com ftopic153510

"The design is empty" - That usually means your design does absolutely nothing, so ISE optimized it all away. Look for a simple bug such as a missing line of code or a wrong signal name somewhere. If you show us your code, maybe someone can help you.

I don't understand "can core can be used directly ... ?"
 

    Matrix_YL

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Matrix_YL

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map:52 - problem encountered processing rpms.

thanks echo47

I make a big mistake , I want to use comparator_v8_0.vhd (behavioral model generated by Core Gen to simulate )as my module directly so ISE can not recognise this core .

It's seems I don't familiar with how to use core gen and instantiate core in my design .Can anyone give me correct steps or some advices on use core gen in ISE ?

these are my steps
1.use core gen to generate core .
2.add *.xco to project .
3.instantiate *.v or *.vhd (generator by core gen as behavioral model to simulate ) in my module


thank you very much
 

sun_yet_san

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comparator xilinx

I just meet the similar problem.
My code is as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Tenbit_Multiplier is
port(mux1,mux2:in std_logic_vector(9 downto 0);
product:eek:ut std_logic_vector(19 downto 0));
end Tenbit_Multiplier;

architecture Behavioral of Tenbit_Multiplier is
begin
process(mux1,mux2)
variable temp1:std_logic_vector(10 downto 0);
variable temp2:std_logic_vector(19 downto 0);

begin
temp2:="00000000000000000000";
for i in 0 to 9 loop
if(mux2(i)='0') then
temp1:="00000000000";
else
temp1:='0'& mux1;
end if;
temp2(10+i downto i):=temp2(10+i downto i)+temp1;
end loop;
product<=temp2;
end process;

end Behavioral;

Anyone can help me?Thanks a lot!
 

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