Xilinx Coding Style for Synthesis and ieee package usage

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Hi All ,

I noticed that most of the coding templates in the vivado user guide and most of the templates available in VIVADO itself use

ieee.std_logic_arith , which is the synopsys package. I know that it should not be mixed with ieee.numeric_std ( in the same file)

So I was wondering if there will be any issue with inference of synthesis constructs if i use only ieee.numeric_std

Please let me know
 

It is OK! The only "problem" you might have is that multi-bit ports of type std_logic_vector in IP blocks need casting if you want to use them as numbers with numeric_std.
Your own entities can use unsigned/signed for such ports instead of std_logic_vector.
 

Both work. People will complain if you use std_logic_arith. That is the main reason to use numeric_std at this point.
 

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