For standard cell comment these in and comment out the BRAM lines - instantiates the ROM modules
FEAT_INFO_RECT0_ROM F0 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_rect0), .we(feat_wea));
FEAT_INFO_RECT1_ROM F1 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_rect1), .we(feat_wea));
FEAT_INFO_RECT2_ROM F2 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_rect2), .we(feat_wea));
FEAT_THRESHOLD_ROM T0 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_threshold), .we(feat_wea));
FEAT_LEFT_ROM L0 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_left), .we(feat_wea));
FEAT_RIGHT_ROM R0 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_right), .we(feat_wea));
STAGE_THRESHOLD_ROM T1 (.addr(class_current_stage), .clk(CLK), .din(), .dout(stage_threshold), .we(stage_wea));
// For FPGA comment these in and comment out the ROM lines - instantiates the BRAMs
//FEAT_INFO_RECT0 bram_feat_rect0 (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea),
// .douta(feat_rect0));
//FEAT_INFO_RECT1 bram_feat_rect1 (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea),
// .douta(feat_rect1));
//FEAT_INFO_RECT2 bram_feat_rect2 (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea),
// .douta(feat_rect2));
//FEAT_THRESHOLD bram_feat_threshold (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea),
// .douta(feat_threshold));
//FEAT_LEFT bram_feat_left (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea), .douta(feat_left));
//FEAT_RIGHT bram_feat_right (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea), .douta(feat_right));
//STAGE_THRESHOLD bram_stage_threshold (.clka(CLK), .dina(), .addra(class_current_stage),
// .wea(stage_wea), .douta(stage_threshold));
parameter num_class = 3; // number of parallel classifiers
parameter last_stage = 21; // last stage number
wire [3:0] scale = IN_SCALE;
reg [7:0] stage_feature; // number of current stage (Max. 213)