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xilinx bram initialisation -reg

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arunshanmugam46

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i created a bram using xilinx core generator.i used readmem command to read the values stored in .mif file generated by core gen.The problem is that access time is high to access a single location in bram...how to reduce the access time without using readmem command
......
 

jimwu88

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What exactly do you mean by "access time of readmem is high"? readmem is used to initialize the memory.

i created a bram using xilinx core generator.i used readmem command to read the values stored in .mif file generated by core gen.The problem is that access time is high to access a single location in bram...how to reduce the access time without using readmem command
......
 

arunshanmugam46

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What exactly do you mean by "access time of readmem is high"? readmem is used to initialize the memory.

since we are reading memory from an external data file while implementing in FPGA.............access time is high as obtained from synthesis report..
 

jimwu88

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OK. So is it that the synthesis tool takes a long time to read the external data file? If yes, how big is the data file? Can you post snippets of the synthesis report showing the long synthesis time during readmem function?

since we are reading memory from an external data file while implementing in FPGA.............access time is high as obtained from synthesis report..
 

arunshanmugam46

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hi all,
i am implementing ldpc decoder in verilog.i am in need of storing 2304 values in memory that is required till the end of the program .How to save those values without using the command reg[0:7]mem[0:63].My friend suggested bram but i am not clear with it.when i searched in net for bram i got the following code.please help me for storing those values in bram..i have attached my friends sample code too.
Code:
For standard cell comment these in and comment out the BRAM lines - instantiates the ROM modules
FEAT_INFO_RECT0_ROM F0 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_rect0), .we(feat_wea));
FEAT_INFO_RECT1_ROM F1 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_rect1), .we(feat_wea));
FEAT_INFO_RECT2_ROM F2 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_rect2), .we(feat_wea));
FEAT_THRESHOLD_ROM T0 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_threshold), .we(feat_wea));
FEAT_LEFT_ROM L0 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_left), .we(feat_wea));
FEAT_RIGHT_ROM R0 (.addr(current_feature), .clk(CLK), .din(), .dout(feat_right), .we(feat_wea));
STAGE_THRESHOLD_ROM T1 (.addr(class_current_stage), .clk(CLK), .din(), .dout(stage_threshold), .we(stage_wea));

// For FPGA comment these in and comment out the ROM lines - instantiates the BRAMs
//FEAT_INFO_RECT0 bram_feat_rect0 (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea), 
// .douta(feat_rect0));
//FEAT_INFO_RECT1 bram_feat_rect1 (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea), 
// .douta(feat_rect1));
//FEAT_INFO_RECT2 bram_feat_rect2 (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea), 
// .douta(feat_rect2));
//FEAT_THRESHOLD bram_feat_threshold (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea), 
// .douta(feat_threshold));
//FEAT_LEFT bram_feat_left (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea), .douta(feat_left));
//FEAT_RIGHT bram_feat_right (.clka(CLK), .dina(), .addra(current_feature), .wea(feat_wea), .douta(feat_right));
//STAGE_THRESHOLD bram_stage_threshold (.clka(CLK), .dina(), .addra(class_current_stage), 
// .wea(stage_wea), .douta(stage_threshold));

parameter num_class = 3;	// number of parallel classifiers
parameter last_stage = 21;	// last stage number

wire [3:0] scale = IN_SCALE;

reg [7:0] stage_feature;	// number of current stage (Max. 213)
 

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