I don’t know what tool you use.
If you use Cadence Virtuoso as Design Framework,
open Layout>Options>Display Options
Really??? Can I use grid 0.0000001u?Set any value you like.
For your question, you can found it in PDK document called PhysicalDesignRule.Thanks for your reply. Yes I know this. I want to know what should be the X snap spacing and y snap spacing. What values should it be. I am using cadence silterra 130nm.
Yes, as far as you don’t care about off-grid.Really??? Can I use grid 0.0000001u?
Really??? Can I use grid 0.0000001u?
If you not sure, don't tell so assured like that.
For your question, you can found it in PDK document called PhysicalDesignRule.
It's specified in General Layout Requirement - Layout Grid part (I referenced in silterra180nm and supposed the same on silterra130nm).
I think the value is 0.005u.
Yes, as far as you don’t care about off-grid.
Set any value according to your need.
I cant find the physical design rules. In the PDK documents I have only four files which is related to smart tool kits list of layers and reference manual which is not providing the design rules. Thats what the issue is. From where I can get it now?
I dont know why my pdk does not contain design rule document.
But I want to fabricate the chip. I dont know why my pdk does not contain design rule document.
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You have silterra 130nm?
your_pdk_path/silterraC13/techfile.tf
techParams(
;( parameter value )
;( ---------- ----- )
( maskGrid 0.005 )
( cadGrid 0.005 )
( drcGrid 0.005 )
( mfgGrid 0.005 )
( scale 1.0 )
Because it is incomplete. You should complain to someone up the chain. You can't design without documentation... snapping is just ONE tiny issue, you will face another MILLION issues.
Of course, wrong.M I right?
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