Wrong value outputted from AD

[gongyuwei]

Hi, I am designing a data acquisition circuit. The AD IC I use is AD9628. In the test, I found that the digital output of AD was always a wrong constant value, and this value was followed by a right value, and then this wrong value, then right value........ It was so weird. Did anyone encounter this event?

 

[chuckey]

I did a Google on AD9628 and got the Analog site - Its a very complicated chip:???: and I suspect that you are talking about serial data and you have not set the multiplexer up properly.
Frank

 

[gongyuwei]

Do you mean that SPI interface of AD was used uncorrectly?

 

[cl10greg]

What speed are you reading the digital output at with your main controller and what frequency do you have the AD sampling? Is the wrong value always the same wrong value? What digital output mode are you using? What main controller and communication protocol are you using?

 

[gongyuwei]

I am sorry, I did not describe my problem in detail. I tested my circuit today, and let me describe my problem again!

I use Spartan6 FPGA to receive the digital output of ADC. AD sampling frequency and the reading speed of FPGA are all 100MHz. The wrong value is always the same, and it is the most weird thing to me. The output mode used is Parallel CMOS mode. The communication protocol is just synchronous receiving of data and clock.

The OPA, PLL IC and ADC are designed in a small board, and FPGA is designed in another mother board. The mother board receives the digital output of ADC and sends sampling clock to the small board. The two board are connected with a two-row 2.54mm-spacing through hole connector. According to my test result, I found that I maybe not use enough ground connection for return current in connector. When FPGA sends differential clock through connector, there are some noise in the analog input of ADC. However, this problem does not seem to result in the wrong constant output value.

 

[gongyuwei]

Hi, I tested my board. I found that there is a 100MHz noise on the both of the differential input of ADC. When I powered down the ADC, the noise went away too, in which case the input sampling clock existed. Therefore, I think that the noise is not the interface from this clock and may from the internal of ADC. The noise is about 50mV. Can someone tell me whether this noise is from the switching of the sample and hold capacitor of ADC, and give me some advice？