rsrinivas
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Hi all
how do i write a wrapper to interface a fifo to AHB.
i have the fifo signals namely
fifo_data
fifo_reset;
fifo_clk;
fifo_full;
fifo_empty
the fifo code is in verilog.
:idea:
thanks in advance
regards
srinivas
how do i write a wrapper to interface a fifo to AHB.
i have the fifo signals namely
fifo_data
fifo_reset;
fifo_clk;
fifo_full;
fifo_empty
the fifo code is in verilog.
:idea:
thanks in advance
regards
srinivas