Can we use tasks (or functions) in sequential always blocks in synthesizable verilog code??
I couldnt find any proper set of guidelines or rules describing the use of tasks and functions for synthesis.
I know we are not supposed to use timing control statements such as @, wait, #delay, etc in tasks, and we must use blocking assignments, and use tasks to describe combinatorial logic only and not sequential.
But what happens if we declare this combinatorial task/function, and then use it inside a clocked always block.
e.g. I want to make a pipelined adder with 2 stages which adds a & b in first stage, then adds c to the result in stage 2. Here's the code
Code Verilog - [expand] |
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| input a,b,c;
output d;
reg stage1, stage2, p,q;
always @(posedge clk)
begin
add (a, b, p);
stage1 <= p;
add (stage1, c, q);
stage2 <= q;
end
assign d = stage2;
task automatic add (input x, y, output z);
begin
z = x + y;
end
endtask
endmodule |
Is this a synthesizable code??
I wrote a similar design, but quite complex, which is not giving any synthesis errors/warnings. But I dont know if it would produce any simulation mismatches??
I tried searching for a straightforward answer regarding synthesis of tasks/functions but nowhere found a clear description. Some texts say that we can use the outputs of tasks in synchronous always blocks thats all i found.