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Writing a long vector input port to an array

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shaiko

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We have the following entity with port "I_DATA" being a long vector of a generic width.
Even though "I_DATA" is a signle port it's logically divided to a generic number of words (G_DEPTH) and each word is of a generic width (G_WIDTH).

Code:
entity memory is

generic
( 
	G_WIDTH : 	unsigned ( 31 downto 0 ) := to_unsigned ( 8 , 32 ) ;				-- width of each memory cell
	G_DEPTH : 	unsigned ( 31 downto 0 ) := to_unsigned ( 4 , 32 )  				-- number of memory cells
) ;							

port							
( 							   
	I_CLOCK :  in std_logic ; -- global clock  
	I_RESET_GLOBAL : in std_logic ; -- global reset  
	I_RESET_LOCAL : in std_logic ; -- local reset	
	I_WRITE : in std_logic ; -- write request 			
	I_DATA : in unsigned ( ( to_integer ( G_WIDTH ) * to_integer ( G_DEPTH ) ) - 1 downto 0 ) -- input data    
) ;       

end entity memory ;
Inside this entity I want to write convert I_DATA to an array as follows:

Code:
subtype word is unsigned ( to_integer ( G_W ) - 1 downto 0 ) ; 		
type array_word is  array ( 0 to to_integer ( G_DEPTH ) - 1 ) of word ; 
signal temp_memory : array_word ;
signal memory : 	array_word ;	


for_loop: for index in 0 to ( to_integer ( G_DEPTH ) - 1 ) 
loop
	temp_memory ( index ) <= I_DATA ( ( to_integer ( G_WIDTH ) - 1 + ( index * to_integer ( G_WIDTH ) ) ) downto ( index *  to_integer ( G_WIDTH ) ) ) ;
end loop ;		


writing_to_memory : process ( I_CLOCK , I_RESET_GLOBAL ) is
begin
	if I_RESET_GLOBAL = '1' then  
		memory <= ( others => ( others => '0' ) ) ;
	elsif rising_edge ( I_CLOCK ) then 				
		if I_RESET_LOCAL = '1' then
			memory <= ( others => ( others => '0' ) ) ;
		elsif I_WRITE = '1' then	
			memory <= temp_memory ;
		end if;
	end if;	
end process writing_to_memory ;

Will the above work ?
 

std_match

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I guess it will work, but why not define the type "word" in a package and have the port as an "array of word"?
The code that use your entity must know the definitions anyway. It is better to have them in a package than having them duplicated.
 
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    shaiko

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shaiko

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Is there a way to avoid the "temp_memory" declaration and to define the concatenation in a synchronous process ?

- - - Updated - - -

Is there a way to avoid the "temp_memory" declaration and to define the concatenation in a synchronous process - something like this:

Code:
writing_to_memory : process ( I_CLOCK , I_RESET_GLOBAL ) is
begin
	if I_RESET_GLOBAL = '1' then  
		memory <= ( others => ( others => '0' ) ) ;
	elsif rising_edge ( I_CLOCK ) then 				
		if I_RESET_LOCAL = '1' then
			memory <= ( others => ( others => '0' ) ) ;
		elsif I_WRITE = '1' then	
			for_loop: for index in 0 to ( to_integer ( G_DEPTH ) - 1 ) 
                                       loop
	                               memory ( index ) <= I_DATA ( ( to_integer ( G_WIDTH ) - 1 + ( index * to_integer ( G_WIDTH ) ) ) downto ( index *  to_integer ( G_WIDTH ) ) ) ;
                                       end loop ;		
                          end if;
	end if;	
end process writing_to_memory ;
 

std_match

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The for loop in your first posting must be in a combinatorial process.
"for generate" should also be possible.
 

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