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"work" library for VHDL

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Advanced Member level 4
Feb 16, 2015
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Is it possible to refer to the default "work" library within a file that is compiled into a non-default library? The LRM briefly says that "work" is the "current working library". This would make sense if you wanted to move some existing code that only used references to "work" into a different library as no files would be modified. However, I don't see how to specify the default "work" library vs the current "work" library.

I have not understood the Q completely, but will try to answer it as much as possible.

Is it possible to refer to the default "work" library within a file that is compiled into a non-default library?
What is the necessity for that?

However, I don't see how to specify the default "work" library vs the current "work" library.

I use VCS of Synopsys, so my will be specific to that.
Take a look into the synopsys_sim.setup file created in your compilation dir. What I have seen in my case is that WORK is mapped to WORK in this file. I think this is playing the trick it needs to do (I am not 100% sure about this though).

Given below is an excerpt from my synopsys_sim.setup file.
--VCS MX setup file

--Mapping default work directory 

DEFAULT : work
axi_iic_v1_02_a_proc_common_v3_00_a : axi_iic_v1_02_a_proc_common_v3_00_a
axi_iic_v1_02_a_axi_lite_ipif_v1_01_a : axi_iic_v1_02_a_axi_lite_ipif_v1_01_a
axi_iic_v1_02_a_interrupt_control_v2_01_a : axi_iic_v1_02_a_interrupt_control_v2_01_a
axi_iic_v1_02_a : axi_iic_v1_02_a
work : work

I had compiled the Xilinx AXI IIC VHDL IP along with other VHDL files whose default library was WORK. For the axi iic IP, they were compiled under axi_iic_* library. This file can be manually edited, but be careful of what you are doing else compilation will fail. Note that WORK is the default library. This file shows the relation between logical mapping and physical mapping.

Hope this is useful to some some extent.
Last edited:

In Modelsim you can map "work" like any other library.
I have also used code that everything was referenced as "work" to reference stuff within that library, then within the main body, it was given a specific name:

use work.lots_of_things_package.all;

vmap some_new_library library1_path

....File 2
library some_new_library
use some_new_library.lots_of_things_package.all;

TrickyDicky's post makes me remember, it is very easy if you are using ModelSim. The vmap command takes care of stuff in the synopsys_sim.setup file. Life is a bit difficult for me as I use Synopsys VCS. I had to manually edit the synopsys_sim.setup file for the entire design to work.

After the post about configurations and direct instantiation of entities, I remembered a problem I had with libraries maybe two years ago. I remember that some design teams used libraries a lot in older code, then stopped using them in newer code. I also noticed that different tools handled libraries a little differently. After looking at this and google, I think the issue was that I had expected "work" to refer to a library -- similar to how it is presented in tools.

The issue I recall was that some commonly used code was placed into "work", but then couldn't be referred to within another library because "work" would mean something different. Because existing code frequently referred to the common code using, and because the synthesis tool only allowed a file to be in one library, the use of libraries was made more difficult and eventually new code just assumed everything was in "work".

I wish I had known this for some of the coregen VHDL cores that gave some entities the same name but with different ports...

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