wired-or logic in VHDL - please correct me

[rajakash]

wired-or logic

hi,,,

for example , if the vhdl code is like this
architecture beh of buff is
begin
y<=a;
y<=b;
end;

how can i add the wired-or logic in this?and i have done the same condition like below

library ieee;
use ieee.std_logic_1164.all;
package wire is
type logic_level is (L, Z, H);
type logic_array is array (integer range <>) of logic_level;
function resolve_logic (drivers : in logic_array) return logic_level;
subtype resolved_level is resolve_logic logic_level;
end wire;
package body wire is
function resolve_logic (drivers : in logic_array) return logic_level is
begin
for index in drivers'range loop
if drivers(index) = L then
return L;
end if;
end loop;
return H;
end resolve_logic;
end wire;



library ieee;
use ieee.std_logic_1164.all;
use work.wire.all;

entity en7407 is
port(a,b:in logic_level;
yut logic_level);
end;
architecture beh of en7407 is
signal int:resolved_level:=H;
begin
INT<= a;
INT<=b ;
y<=INT;
end;

is it correct?

plz help me..