wired- or/and functions in vhdl

[rajakash]

wired-ro/and in vhdl

hi,

y<=a and b;
y<=a or b;

how to do wired or/ and for this function. is there any syntax in VHDL like wor in verilog?

plz help me.

 

[eChipDesign]

Re: wired-ro/and in vhdl

The signal should be declared of type 'resolve_logic'.

signal y: resolve_logic;


This should solve a wired-or.

Added after 6 minutes:



This could be how to imply a wired-and

type logic_level is (L, Z, H);
   type logic_array is array (integer range <>) of logic_level;
   function resolve_logic (drivers : in logic_array) return logic_level;
   subtype resolved_level is resolve_logic logic_level;

   function resolve_logic (drivers : in logic_array) return logic_level;
   begin
      for index in drivers'range loop
         if drivers(index) = L then
            return L;  --if any value is L then return L (makes this a wired and)
         end if;
      end loop;
      return H;
   end resolve_logic;