Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Based on my understanding, since the (W/L)s of both upper PMOS & lower HV NMOS are the same, the current-mirror structure makes the current running in each circuit branch be the same, which should be equal to IBP.
Then, we can get Vgs1+IBP*Rs= Vgs2. Therefore, we can get IBP=0.
It seems that this supply-insensitive biase generator could not work. Is there sth wrong with my deduction? could u point it out for me?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
