[SOLVED] Will SVA be normally ignored by synthesis tools?

[layowblue]

Hi all

I thought SVA would be automatically identified and ignored by synthesis tools, but today I got a mail from the synthesis guy saying the SVA lines broke synthesis flow.(The synthesis tool is RTL Compiler)
I did fix it by putting some macro definition to filter out those SVA lines in the RTL.
But I'm still curious about why RC is doing this.
1) Does anyone know if DC would do the same, namely reporting synthesis error upon SVA lines?
2) Are there some settings insdie RC/DC to ignore SVA lines without having to mask them from the synthesis scope?
3) Is there any golden reference from IEEE 1364-2001 saying anything about the SVA VS synthesis?

Thanks a lot
Leo

 

[dave_59]

There is no standard from IEEE that specifies which constructs should be synthesizable, or which constructs should be ignored in SystemVerilog. That is up to each synthesis vendor. DC ignores them.

 

[layowblue]

Thanks Dave for the quick reply.
Do you know of any possible parameter setting in RTL Compiler that can be used to ignore those SVA lines?

 

[dave_59]

You'll need to ask someone at Cadence.

 

[layowblue]

Actually, it turns out to be that the guy was not doing synthesis, he was using a CDC tool that complains about the SVA lines.
I tried myself to synthesis SVA-embedded RTL using RC, and there is NO problem for it.

Thanks Dave again for the care.