will HVT cell affects RVT cell when they are placed closely

[zhangljz]

Hello everyone,

I am designing a layout that there are RVT and HVT mixed together. There are several HVT cells which are close to RVT cells, the space is around 1um.

If the HVT cells convert to RVT, the design is symmetric, while to reduce power consumption HVT cells are used. The question is if HVT cell will affect RVT cell layout matching???

BTW, what is the difference between HVT and RVT during manufacture? Only the dopping concentration ?

Thank you

 

[artmalik]

Well mixing VT doesn't have any impact on the manufacturing side, they are legal. The main issue is with process tracking....as temp,voltage,process changes the delay through each of the VT does scale accordingly. mixing of VT's is not a good idea in analog design because the idea of symmetry is lost. you can use mixed VT designs when you are sure that variation wont impact the performance. For example if there control signal that can be HVT because you are only interested in the DC value of signal and not the timing. Run some monte carlo simulations to see the variation in performance.

 

[dick_freebird]

I would expect that the foundry has already set the
well-species-spacing rules to preclude any autodoping
effects variability. I expect the imlants are relatively
light and subsurface anyhow, not to mention they are
capped off by gate ox and poly where it counts. You
might look for design rules on minimum RVT-HVT implant
spacing, for characterization collateral on this topic,
and see how your actual layout spacing compares to
groundrule minimum.

If your layout style is such that the closest approach
is still on the other side of a S/D region, then you can
forget about it altogether.

 

[zhangljz]

Hello dick,

From DRC rule, the minimum spacing between RVT and HVT is 0.18um. The actual spacing in layout is about 1.5um. The HVT is at diagonal direction of RVT S/D region. Will this spacing enough?