Will decoupling capacitors cause radiated emission

[newbie_hs]

I am debugging a 6 layer board for RE issue and the stackup is (S G G P+G G S).This is a 6 layer board.
The microcontroller is present in TOP(L1) layer and decoupling capacitor is placed in bottom layer(L6).

I was told that "When you decouple through vias, you are always going to get the IO switching signals
producing voltages across the impedance of the vias and this noise is then on the whole plane"

May I know how this is happening?

For BGA's we used to keep decoupling capacitor in bottom layer only.

 

[FvM]

I don't understand which coupling path is suggested by the statement. Via inductance adds to component pin and trace inductance and slightly increases ground and supply bounce. But why would it increase plane noise level?
On the other hand, injecting current into a plane between distant points creates a kind of patch antenna and potentially makes the plane radiate. The effect doesn't specifically depend on vias but the current distribution pattern.

 

[newbie_hs]

Thank you.
The decoupling path here I mean is Decoupling capacitor for Microcontroller VDD(Power supply rail)
The controller is placed in TOP and the Decoupling capacitors for this controllers VDD rail is present on bottom layer L6

 

[KlausST]

Hi,

"Will decoupling capacitors cause radiated emission".
Yes. It is AC current thus it is causing an AC magnetic filed. You can´t avoid it.

BUUUUUUT: the question needs to be:
--> Is the radiation higher with or without the decoupling capacitor.
Or in your case:
--> Is the radiation higher when the capacitor placed on the TOP or BOTTOM layer?

And these questions are rather difficult to answer.

****
On a good PCB layout a capacitor will reduce radiation.

Why: Two important things:
1) current runs in a loop
2) the loop acts as a (transmittign) antenna

1) the current loop: (Here the HF loop is meant.)
GND_pin of IC - noisy signal path inside IC - supply pin of IC - traces and vias on PCB - decoupling capacitor - traces and vias on PCB - GND_plane - GND_pin of IC
Many people think it`s just a one way path (shown in red), but forget about the return path (black). But the return path helps to compensate radiation.

2) as long as you are not working with very high frequencies the following is true: The bigger the area (enclosed by the loop) the better the antenna, the bigger the radiated power.

*****
A simple method is to just use the PCB layout and (virtually) draw the HF loop for both cases: Capacitor on TOP and on BOTTOM.

Klaus

--- Updated Mar 21, 2024 ---

I don't understand which coupling path

@OP: show the part of PCB layout ... to enable a focussed discussion .. with fast and best feedback for you.

But why would it increase plane noise level?

I agree.
How do you measure noise level of a plane?
A good plane is considered as "the reference".
* Voltage: Voltage measurement usually is done against a reference. Reference - Reference = ZERO.
* Current: as said, you have to include the whole loop. And the smaller the loop, the better the magnetic fieds become compensated.
(current in one direction cause a magnetic filed, but since the current in the return path is in opposite directiion it also causes a magnetic field in the opposite direction, thus they compensate. )

I´d say: when capacitor and IC is on TOP side, and you have a solid GND plane, then the radiation on the BOTTOM side is almost zero. All radiated power is on the TOP side.
But when the capacitor is placed on The BOTTOM side, then you get radiation on both sides of the PCB. But this fact alone does not mean it is better or worse. You have to care about the magnitide of radiation.

Klaus

 

[newbie_hs]

The light blue is my controller and decaps are shown in red.
Below is the PDN

 

[Easy peasy]

the caps are somewhat necessary - take them out and you will have far larger problems

 

[newbie_hs]

Yes cpas are necessary.Here discussion is about it's placement

 

[Easy peasy]

there really is little room for discussion - they must go as close to the power pins as possible ( including 0v pins )

 

[D.A.(Tony)Stewart]

I would use all the tools you have available to either inject /measure /perturb/simulate and measure near field EM to validate your EM problem.

To measure it use a small air-coil magnet wire loop antenna formed on a screw with an SMA connector to 50 ohm coax to Spectrum Analyzer (SA). You can choose the SRF to match your dominant EM frequency to increase sensitivity or choose a broadband one with a higher SRF as a near field EM sniffer probe or buy some. ($)
A crude one just shorts a 10:1 probe (short) ground clip. Then use the coil and SA to locate the strongest signal.

For conducted noise use a cap on Vdd to an SMA to coax to SA or DSO || 50 ohm to measure supply spectral density. Use high quality cable.

Then define the following;
1: EM frequency , amplitude and sub/harmonics or spectral plot far and near field highlighting EM source and suppression level required.
2. Model your uC as a noise source and get the s2p file for your decoupling cap and compute your microvia properties. {LRC, SRF, Zo) with your fave tools.

Estimate and measure your supply current dI/dt and equivalent BW from datasheet. It will be higher than external I/O.

Then consider modeling all the parasitics in the design in a Bode diagram or inject and measure it.

This is a crude model that you can start to use to mimic your layout using S2P of caps and load regulation ESR of supply and imagine all the 25 ohm|| 5 pF switches (or whatever) that conduct in parallel in the uC at the dominant cycle rate with harmonics from the internal risetimes as BW=0.35/Tr
Radiated Emissions will be polarized and proportional to antenna length when << 1/4 wave.
The Falstad Sim allows any passive value tuner with mouse wheel or edit it. for millohms use 0.xxx

Otherwise use a real simulator with real cap S2P files or LTSpice or Pspice or whatever you have.

Opinion
Below is not an accurate model for the PDN, but you can read more here. It is up to you to emulate it as best as you can to try to predict if the vias are a problem. My hunch is if you used a few microvias, it won't be there but perhaps in the choice of decoupling cap ESR or routing of I/O cables with common mode noise from a SMPS feeding your LDO.

More PDN references

https://www.edn.com/optimizing-capacitance-in-power-delivery-network-pdn-for-5g/

Understanding PDN Impedance and Stable Power Delivery

PDN impedance affects power delivery throughout electronic systems, including PCBs. We’ll give you a complete overview of PDN impedance.

resources.pcb.cadence.com

https://www.ti.com/lit/an/swpa222a/swpa222a.pdf

Power Distribution Network (PDN) | Intel

The power distribution network (PDN) design tool is a graphical tool used with all Intel FPGAs to optimize the board-level PDN. Learn more about the model and related tools.

www.intel.com

Analyzing Power Integrity on a Power Distribution Network (PDN)

Shorten Design Cycle Time Using 3D EM Simulation Software

Before physical prototyping, model, analyze, and optimize EM designs with 3D EM simulation software.

resources.pcb.cadence.com

 

[marce]

This is covered in multiple documents, by the likes of Henry Ott, etc.
Many data sheets for more complex devices, often have numerous notes covering the decoupling capacitors. The capacitance of a decoupling capacitor is secondary to the pin/cap loop inductance. The general rule, is the smallest package available, with the smallest possible return loop. For BGA's this is caps directly under the pins, sharing the same via's to the power plane. And best is via in pad, no inductive trace to the via, from the pad.
Inductance must be kept to a minimum. The capacitors are acting as a power source for the devices when switching, They supply the near instantaneous power when switching. Looking at Simultaneous Switching Noise information, will give a wider viewpoint of the EMC/signal integrity issues on a PCB. Don't worry about vias, that much.

There is also power integrity software that will show the impedance of a plane at certain device operating frequencies.

Some basic, and oldish info:

https://www.emcstandards.co.uk/files/part_4_planes_corrected_29_june_17.pdf