I'm going to design a PCB with working voltages up to 1000V and I'm following IEC 60950 standard where the creepage/clearance distances are related to certain pollution level.
The system will work in an industrial environment thus pollution level 3 will apply.
In order to reduce the creepage distances and apply pollution level 1 distances I think it is possible to apply dip coating to our boards however some colleagues sustains that dip coating procedure will not decrease the pollution level to "1".
My thesis is supported by the following phrases on EN 60950-1 (par. 2.10.12 Enclosed and seals parts):
For components or subassemblies that are adequately enclosed by enveloping or hermetic sealing to prevent ingress of dirt and moisture, the values for Pollution Degree 1 apply to internal CLEARANCES and CREEPAGE DISTANCES.
NOTE Some examples of such construction include parts in boxes that are hermetically sealed by adhesive or otherwise, and parts enveloped in a dip coat.
Potting or coating material may be used on PCBs to protect against pollution but also improves the microenvironment of the parts underneath the protection (EN62109-1, 7.3.7.6). When coating is used to reduce the effective pollution degree for the purposes of reduced spacing requirements, it is called a “conformal coating” and, pollution degree 1 applies for the coated area. The potting or coating material must pass a test according to EN60664-3.
You need a Conformal Coating, dipping may provide it... Look up conformal coatings for PCB's. If done correctly you can reduce creepage and clearance gaps. Look at IPC-2221B Table 6-1 and associated text.
For UL it needs to be an approved coating & process. If you use any old thing that can peel off later because the pcb is greasy - or for other reasons - then you cannot claim pollution degree one under the coating ...