Wide band Phase lock loop (PLL)

[RadhikaT]

Hi ,

To design a wide band PLL ,is it only way to Increase Kvco ?

PLL Band width : ( Icp * R * Kvco )/2*pi

In order to not push charge pump to triode region (Icp * R) should not exceed max 2.5 v if PLL Operates on 2.5 v .Only way is to increase Kvco as this equation shows

 

[dick_freebird]

That might be your charge pump limited bandwidth, but the loop
filter would reduce it from there. I'd expect by at least 10X for a
decent phase noise (you have to flatten the pump ripple).

I'm no PLL expert but find it odd that there is no AC term in
your bandwidth equation. You'd think the capacitance on
the charge pump node would be fundamentally limiting.

Now, if you broke the linear single-pole paradigm (say, with
a loop amp that had dual slope, one for near-null and one
for high-error that slews harder, maybe you could realize
a better net bandwidth (if bandwidth is aimed at a frequency-
agile application and not for optimizing some frequency-
static attribute).

 

[RadhikaT]

This equation is almost correct if

PLL is either critically damped or Overdamped.

PLL loop bandwidth is 20 times less than Loop Update Frequency (Fref)

Icp*R is the jump on Vcntl when either of charge pump (UP or DOWN) are on .

one situation happens when UP/DOWN currents are not equal due to statistical or systemtic mismathes.

 

[love_analog]

Not entirely correct, Radhika. Its not ICp*R that needs to be limited to 2.5V. Its vctl.
Vctl is typ set by the cap of the loop filter and the Icp dumped into it. Icp*R is a transient thing every reference cycle (when PLL is locked)

Added after 18 seconds:

Not entirely correct, Radhika. Its not ICp*R that needs to be limited to 2.5V. Its vctl.
Vctl is typ set by the cap of the loop filter and the Icp dumped into it. Icp*R is a transient thing every reference cycle (when PLL is locked)

 

[RadhikaT]

Yes .... I want to say Icp*R is the ripple on Vcntl under locked condition. 2.5v is the highest ripple charge pump can handle with out going to triode if Charge pump operates with zero overdrive and steady state value on integrting Cap is zero.

Can anybody help how to increase PLL bandwidth by keeping Icp*R product as low s possible ??

 

[mosys]

hi radhika,
why you need wide band (are you interested in low long term jitter? ) and how wide it is? and icp*r is not the ripple on control node even in lock condition provided you are working with 3rd order pll...generally for changing bandwidth people use programmable Icp, because Kvco is very difficult to control at least in silicon when compared to Icp control.

Thanks,
Rajasekhar.

 

[RadhikaT]

This is 10GHz PLL in 65nm And Timing jitter < 0.2 pS .It has 10GHz LC VCO .At 10GHz Tank Q is less than 4 .Only option is going ahead with wide band PLL.Analysis shows required PLL bandwidth should be around 10MHz @ 156.25 MHz reference frequency.

Since frequency dividers already working at its full bandwidth ,PLL can't tolerate frequency peaking . So should go for higher damping factor which means higher Phase margin . It means place loop filter second pole at least 10 times away unity gain frequency of PLL.

simple calculation : PLL Bandwidth : 2*pi*10 MHz --- 60 Mrad/s

Loop Filter second pole : 60 M* 10 : 600 Mrad/S ( 1.7 nS Time constant).

Static/dynamic mismatchs associated with Phase Frequency detector and charge pump can be 5% of Reference frequency which can be (0.05/156.25M) : 0.32 nS

if calculate ripple on Vcntl under locked condition after inserting second pole inside loop filter ( Which means PLL is 3 rd order ) : Icp*R ( 1- e^-t/1.7ns ) : Icp*R ( 1- e^-0.32ns/1.7ns) -- Icp*R *0.2 ( 20% * Icp*R)

This much ripple also problematic since Charge pump will be operted with large Overdrive (300 mV) in order to minimize statistical mismatch. It will become even worst if we go for differential charge pump . these are showing little scope to depend on Charge pump current to Extend PLL bandwidth.