For array size 256 it can be completed but for the sizes more than 256 I faced with a long time...
But FPGA is very advanced I am sure it should not be about to low resources...
Can any guide me?
How can initialize a big reg array in verilog?
This has nothing to do with how advanced an FPGA you are using, it has to do with the size of the logic necessary to implement the array.
16-bit values 1024 entries by 2 arrays.
As you named these arrays with an I and a Q in the names, I suspect this is being used as a constant array for something like filter coefficients, which means you are probably later in your usage of this array doing something like this:
x <= data_i_buffer[index];
Once you index into this array you are creating a multiplexer. There are 16 1024-to1 multiplexers required to implement even one of these arrays. Using a simple implementation in a 6-input LUT FPGA you would require:
1st stage: 1024/4= 256 4-to-1 muxes
2nd stage: 256/4 = 64 4-to-1 muxes
3rd stage: 64/4 = 16 4-to-1 muxes
4th stage: 16/4 = 4 4-to-1 muxes
5th stage: 4/4 = 1 4-to-1 mux
With 16 bits in each word to multiplex:
(256+64+16+4+1)*16 = 5456 LUTs
For 2 arrays being used 10912 LUTs are required just to implement the indexing into the array.
From what I've seen these types of large structures generally cause synthesis headaches as the synthesis tools seem to try and optimize the multiplexer tree. If you insist on using registers to store this (instead of a block RAM, which is what you should be storing such an array in) then I would build a structural multiplexer tree, perhaps even using CLB primitives, to reduce synthesis times.
IMO I would limit any logic based multiplexer to 64 inputs or less if possible and anything above that would end up in a RAM block.