vin vin gnd dc 'vdd*0.5'
vip vip gnd dc 'vdd*0.5' ac 1.0
.ac dec 10 1Hz 1GHz
.probe ac vdb(vout) vp(vout)
shaq said:Dear all,
I have a little question that is why we usually set ac=1v during simulate such as dc gain, phase margin and ugbw.
Just like this.
Code:vin vin gnd dc 'vdd*0.5' vip vip gnd dc 'vdd*0.5' ac 1.0 .ac dec 10 1Hz 1GHz .probe ac vdb(vout) vp(vout)
chang830 said:shaq said:Dear all,
I have a little question that is why we usually set ac=1v during simulate such as dc gain, phase margin and ugbw.
Just like this.
Code:vin vin gnd dc 'vdd*0.5' vip vip gnd dc 'vdd*0.5' ac 1.0 .ac dec 10 1Hz 1GHz .probe ac vdb(vout) vp(vout)
It is just for the computation easily. Of course, u can set AC as other values.
Sadegh.j said:I believe that this because we have to make sure that the transistors should not saturate as a result of invalid input amplitude.
shaq said:chang830 said:shaq said:Dear all,
I have a little question that is why we usually set ac=1v during simulate such as dc gain, phase margin and ugbw.
Just like this.
Code:vin vin gnd dc 'vdd*0.5' vip vip gnd dc 'vdd*0.5' ac 1.0 .ac dec 10 1Hz 1GHz .probe ac vdb(vout) vp(vout)
It is just for the computation easily. Of course, u can set AC as other values.
Computation easily? why?
shaq said:Dear all,
I have a little question that is why we usually set ac=1v during simulate such as dc gain, phase margin and ugbw.
Just like this.
Code:vin vin gnd dc 'vdd*0.5' vip vip gnd dc 'vdd*0.5' ac 1.0 .ac dec 10 1Hz 1GHz .probe ac vdb(vout) vp(vout)
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?