RTL at its inception was register transfer level but over time it has taken new meaning. Today the term is loosely used refering to a variety of technqiues. Literally, it should mean any design that involves synchronous movement of data in and out such as registers. But just look at the RTL schematic of your synthesized code for any design. Synthesis tool makers just use RTL to any schematic that has building blocks that could be asynchronous or combinational in nature.
It seems however that RTL when referring to coding means behavioral design. This is how most experienced designers and book writers portray RTL these days. Let's see where the new understanding of RTL takes us in future.
RTL, Register Transfer Level,
Registers are like nodes in design, they break paths into pieces. All your design's like describing the data transfer between registers. That's why it's called RTL.
in RTL methodology, the design activity is made much simple. this is the high level design, we need not to consider the transistor level first, and this of course make life easier.
register transfer lavel (rtl) is the basic unit of digital design in fpga. instead of gate level, fpga prefer logic element (altera) or common logic block (clb) that is based on sram technology with look up table (lut). in such design criteria, rtl level design with mainly dff element is noted to be the basic element of fpga design.
the definition given by delay is the closest to the meaning of RTL today .. don't stuck just to the REGISTER idea .. or as u called Flip FLop .. let's broaden ur view to the meaning of RTL .. nowadays RTL became something like no. of GUIDELINES applied to any language .. for example : the RTL guidelines for HDL imply some rules .. like never use this .. always use that .. and so on .. and the best place to get the RTL guidelines from if ur doing HDL is :
Reuse Methodlogy Manual .. it's close to perfection ..
P.S. it's downloadable from here .. just search for it 8O
Of course, RTL is an acronym of "Register Transfer Level" and it means that the main things in design are registers. But, I wonder whether we can recognize that a VHDL source is wrote in RTL or in the other levels.
Somebody can give me some characterizations to identify this problem or some documents to read?