why vth shifts wrong when L gets smaller in Cadence ADE

[glinsana]

hi,guys
i am really confused about Vth right now

here is my story
I have an pmos, it's model is from SMIC 0.13um
and use BSIM3v3, Cadence ADE,spectre for simulation

I choose to save DC operating point in order to save vth for my pmos

but I found when L gets smaller, vth gets bigger.

e.g.:L=130nm Vth=-430.9mV or so
L=400nm Vth=-400mV

How does this come out?
can anyone help me ?;-)

 

[erikl]

... I found when L gets smaller, vth gets bigger.

L=130nm Vth=-430.9mV
L=400nm Vth=-400mV

|Vth| gets smaller!

 

[dick_freebird]

There are "short channel effects" and there are "reverse
short channel effects" and the model params are only an
attempt to fit the reality.

 

[glinsana]

|Vth| gets smaller!

Vth gets bigger…… by which i mean |Vth|

- - - Updated - - -

There are "short channel effects" and there are "reverse
short channel effects" and the model params are only an
attempt to fit the reality.

I take them into consideration too.
But the results i got yesterday by Id-Vgs DC sweep test brings a result that proves |Vth| should get smaller when L gets smaller.I think it is the right "short channel effect",isn't it?

 

[erikl]

Vth gets bigger…… by which i mean |Vth|

Yes, you're right, sorry!