Why Vsin of analoglib in Cadence behaves in a different way??

[shaikss]

Hi,

Pls check the attached figure.
I have given Vsin of 600mV amplitude to an rectifier to pump ac voltage.
When I plot RF+ and RF-, which are two terminals of Vsin, I could see the plot in the attached way.
I expected that all the positive peaks of RF+ and RF- are at 300mV and -300mV respectively. But simulation plot is different.
Can you pls tell me why it is so?

 

[dick_freebird]

We don't know what your circuit looks like, but the
point of is sounds like you're pumping charge and
that is indeed what's going on. The pumped charge
evidently is pulling the common-mode of the differential
source.

 

[shaikss]

We don't know what your circuit looks like, but the
point of is sounds like you're pumping charge and
that is indeed what's going on. The pumped charge
evidently is pulling the common-mode of the differential
source.

I have attached the circuit snapshot and snapshot of the circuit from cadence. RF+ and RF- are the terminals of the voltage source Vsin.
Can you pls explain why it is behaving so?
As I mentioned earlier, I expected that all the positive peaks and negative peaks will be at 300mV and -300mV respectively when an amplitude of 600mV is given for Vsin.
Pls let me know where I was wrong and what needs to be done.

 

[dick_freebird]

Nowhere does there appear a ground reference or any
path to it. Therefore you cannot expect any particular
common mode position to be maintained; any resistive
path, including simulator-applied conductance meshes,
or even numerical error residue, could let the solution
"drift".

 

[shaikss]

Nowhere does there appear a ground reference or any
path to it. Therefore you cannot expect any particular
common mode position to be maintained; any resistive
path, including simulator-applied conductance meshes,
or even numerical error residue, could let the solution
"drift".

What should I do? Moreover, I see very small output current at the output for I stage also. I am not getting how to make the circuit more efficient. I tried to vary the widths of MOSes. But there is not much improvement. There is a current of around 2.5mA at the input side and 5uA of current at the output. How should I maximize the current at the output? Please suggest me. I am in desperate need of help. I need to see max efficiency. I am getting max efficiency of 29% for stage 1. I am trying to simulate the circuit by following reference paper.I have attached the paper and current waveforms too.