why use SVA in a model/predictor based design?

[prashantsid]

Hi all,

I have a model or predictor based verification environment.
Each and every signal from the DUT is compared with that of the model to check the correctness of the design.
Now my question is, in this type of verification environment where the model keeps a check on all the functionality and the timing specifications covering each and every pin of the IP, do i need to write assertions?
BTW i am currently in verification team. please explain the importance/relevance of assertions for both designers as well as verifiers.

Thanks a ton for your time.

 

[dave_59]

You should see https://verificationacademy.com/courses/assertion-based-verification