why to avoid gated clock while inserting scan chain?

[biju4u90]

Why should we avoid gated clocks while inserting scan chains in our design? Is it a must that clock should be a primary input?

 

[maulin sheth]

Generally we avaoid gated clocks as we need controllability for clocks also. If design have a gated clocks, we should have a full controllability of that gated logic. And if it is general clock gating cell, tools are able to understand clock gating cell structure but it is also under control during shift mode. So, to control the clock in shift mode, we avoid gated clocks.
Hope it helps.

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Regards,
Maulin