Why the DRC violation happened in DC synthesis?

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ASIC_intl

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Hi

In design compiler I found after synthesisi the timing is met but the DRC s (max_transition, max_capacitance) are being violated for some of the nets. Why are there DRC violation.

Regards.
 

dc DRC

You probably need to add constraints to your design so Design Compiler will synthesize around them and produce a DRC clean netlist.
 

Re: dc DRC

how did you perform this DRC? What tool was used? Usually, if DRC is not meet, synthesizer stops and does not proceed to the cells mapping / timing optimization phase. Am I wrong?
 

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