why the differential output signal not symmetric

[prcken]

Hi,
I am designing a buffer for very high speed clock. let's say 12GHz. A signal at this high-speed is sine-like waveform.
It's weird that the output of the signal are not symmetric.
Did anyone have this problem before?
I am sure It's not the problem of settling or simulation resolution.
Thanks!

 

[crutschow]

It looks like the top of the waveform is being clipped.

 

[Audioguru]

The top of the waveform at the collectors of the upper transistors is clipped because the upper transistors are almost cutoff and any load will cause a voltage divider making the clipping worse.

 

[prcken]

Yes. but it's fine for this large-signal case.

 

[D.A.(Tony)Stewart]

Increase bias current to bring collector current up and shift average voltage down for same swing to get better symmetry.

 

[KlausST]

Hi,

i can not find CKin, CKinb, n23 and n24 in your schematic. So I don´t know where the signals refer to.


In the schematic a see VDD25, if tihs is "VDD = 2.5V" then a node voltage of 2.4V is about at it´s limit.

Klaus

 

[prcken]

Increase bias current to bring collector current up and shift average voltage down for same swing to get better symmetry.

Yes, increase the current to lower the common mode voltage helps!
Thank you!

- - - Updated - - -

Hi,

i can not find CKin, CKinb, n23 and n24 in your schematic. So I don´t know where the signals refer to.


In the schematic a see VDD25, if tihs is "VDD = 2.5V" then a node voltage of 2.4V is about at it´s limit.

Klaus

Hi Klaus,

Sorry for the confusion. CKin CKinb are the input pair signal, and n23, n24 are the differential outputs in the schematic i showed.

Yes, it is 2.5V power supply. I think it didn't go to 2.5 due to the speed limitation.