Probably both processes used the same BOX with the same electrical permittivity and the same distance between metal paths and substrate.
Notice that You mentioned about M1 capacitance per unit area.
Everything is possible but nobody mixing two quite different processes - it's inpractical.
High-K processes was invited to overcame problems with very thin gate oxide, like tunnelling current, breakdown voltage, etc. But everything above transistors (burried oxide, metal layers distance) are quite similar.
In each technology process You have two types of dielectric. Gate oxide (in old technologies it was only SiO_2 or SiON, while in high-K it's stack of two dielectrics like SiON and HfO2) and burried oxide for metal layers isolation. Of course we need high electrical permittivity materials for gate oxide for high current gain factor and low permittivity materials to avoid capacitive coupling between metal paths.
If You want to study about processes, I think the best knowledge mines are Solid state electronics, transactions on electron devices and electron devices letters journals.
From 180nm to 32nm, although space is smaller, k is lower and metal thickness is thinner too. So, the capacitance would be not larger.
Ex., M1 thickness 5300(180nm) vs 900(28nm); k value 3.7(180nm) vs 2.63(28nm)