Why should we have non-blocking statements in an always block?

[kunal1514]

Hi All,

I am having a query for all that

As we know it is recommended that better have Non - Blocking Statements in an always block . Why?

Can any body tell me what's the reason behind this

Regard's

Kunal Mishra

 

[asicengineer1]

Always Block

actually, u can have blocking statements in always block if u r modelling combo logic.

 

[nanda_kishore]

Re: Always Block

For sequential blocks... the blocking statements ends up in a infinite loop and hang up the simulation.. In synthesis they end up in the latches..

for example :

consider simulating these codes..

always @ (posedge clk)
begin
a = a+1;
b = a;
end

and this...

always @ (posedge clk)
begin
a <= a+1;
b <= a;
end

and find the difference for yourself ..... Good Luck

 

[bbgil]

Re: Always Block

Verilog supports two types of assignments within always blocks, with
subtly different behaviors.
* Blocking assignment: evaluation and assignment are immediate
*Nonblocking assignment: all assignments deferred until all right-hand
sides have been evaluated (end of simulation timestep)
Sometimes, both produce the same result. Sometimes, not!
Guideline:
*use nonblocking assignments for sequential always blocks
* use blocking assignments for combinational always blocks

Hope this helps.

 

[yln2k2]

Re: Always Block

Pretty good explanation by previous reply .
Just I want to add one more point .
synthesis results are what design intent but simulator understands in a diff way so there is a possibility getting diff results from simulation and netlist ...


Thanks & Regards
yln

 

[kunal1514]

Re: Always Block

What is Simulation Time Strap and how do we calculate it.

It's very important.


Regard's

Kunal Mishra

 

[rajkishore12345]

Re: Always Block

I would like to add one more point
Use Verilog nonblocking assignments in the sequential always block.
Reason:Helps avoid hold-time problems when driving most gate-level
models from an RTL model.

 

[Sanyok1978]

Re: Always Block

Difference between blocking and non-blocking?
The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are distinguished by the = and <= assignment operators. The blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. For example, the following Verilog program

// testing blocking and non-blocking assignment

module blocking;
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;

$display("Blocking: A= %b B= %b", A, B ); A = 3;
#1 A <= A + 1; // non-blocking procedural assignment
B <= A + 1;
#1 $display("Non-blocking: A= %b B= %b", A, B );
end
endmodule

produces the following output:
Blocking: A= 00000100 B= 00000101
Non-blocking: A= 00000100 B= 00000100

The effect is for all the non-blocking assignments to use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the current time unit. This reflects how register transfers occur in some hardware systems.
blocking procedural assignment is used for combinational logic and non-blocking procedural assignment for sequential

 

[mohammed.peer]

Re: Always Block

You can use both blocking and nonblocking assignments in always block.But for better results follow some guide line..

1. For sequential block use nonblocking.
2. For Combinational logic use blocking assignment.
3.Do not mix blocking and nonblocking in single always block.

 

[vlsichipdesigner]

Re: Always Block

Check this web page for a Good coding verilog styles
https://www.vlsichipdesign.com/verilog_coding_styles

 

[vizpal]

Re: Always Block

always block is mailny used to model sequential logic..

always@(posedge clk)
..........
..........

This means that whole of the sequential module is sensitive to change in the clock, and that every signal in the always block must respond to change in clock. So, its better to use non-blocking operator inside the always block and hence all the statements are executed concurrently(pure sequential)..... If blocking operator would be used then chances are that a particular statement may block the other statements from being executed..

 

[xlxlyu]

Always Block

because non - Blocking Statements may generate some latch you don't want to