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Why positive S11 parameters when simulating a via ?

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Full Member level 5
Nov 28, 2009
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I get positive S11 when trying to simulate a trace with 2 vias. This is very confusing for
passive stuff. It's only about +0.28dB, but anything positive has got to be wrong!

This piece of trace is one of a pair intended to connect to the source tabs of a GaAsFET HEMT.

The simulator uses method-of-moments for planar EM simulation.

If anyone knows, or has seen this before, I could use a hint as to how to progress.
Is it the meshing? Something to do with frequency interpolations maybe?


Thanks if you can help..

With "positive S11 parameters", you mean |S11| > 1, a vectorial S11 value outside the unity circle?

Yes indeed! |S11| >1 puts it outside the circle. Sorry - I should mention also the vertical scale is S11 mag in dB

It is wrong, because in a passive thing, even a 100% total mismatch should never produce a reflection greater than that offered in.

Any S11 that gets outside the unity circle is instant instability, negative resistance oscillation, etc. S21 is >1 if there is gain. We always hope that S12 is so far below that it is not a problem, through a GasFet HEMT with gain even at 20GHz.

I need it to work 8GHz to 9Ghz. You can imagine how unhappy I am that the answers have suddenly gone into never-never land!

My test circuit does not even have a "Port2". It's just a little copper trace and 2 vias through to ground-plane. The substrate is low-loss 0.762mm (20mil) thick, Dk=3.5. The via holes are 0.4mm (15.7mils). The copper is 1 Oz 0.035mm (about 1.33mils).

I think your sim setup is wrong. Can you post how you setup or simulation and which program?

You are right about the simulation setup must be wrong. This is one of the downsides of doing such things on borrowed kit.

That simulator was Ansoft Designer, and I did try taking the accuracy up to level 4, and setting the mesh size so that even the trace metal thickness would be over the minimum. We also went for full discrete frequency points instead of "interpolated". The result was a slightly different shape, but still going positive. Not by much (0.02dB), but still a mess.

None of us has HFSS, but we did shamelessly befriend a new pal who drives CST, and asked her to help. A harmonic balance simulation quickly yielded the correct answers. We can now "tune" the inductance by setting down more vias in a row. We get a set of S-Parameter sub-circuits that we can place in the source ports of the HEMT FET.

Maybe life is too short to knock ourselves out going after why the method_of_moments fails on this one, and I would not willingly waste your time, but thanks for your kind reply.

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