[SOLVED] Why PLL is a negative feedback system?

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bladewade

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A question in Razavi's book--RF Microelectronics. I don't understand the answer it gives: The phase detector provides both negative and positive gains. Thus, the loop automatically locks with negative feedback.
 

I think, you can answer the question yourself by looking at slope of the transfer characteristic of the phase detector and assume different start phases for the lock process.

I don't have the book, but the answer sounds very visual.
 
I think I get it now. Thanks for your help.
 

Another question: could you please explain to me why retiming flipflop can remove divider phase noise? Is it because retiming flipflop kind of eliminate the uncertainty brought by divider jitter?
Thank you in advance.

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FvM said:
I think, you can answer the question yourself by looking at slope of the transfer characteristic of the phase detector and assume different start phases for the lock process.

I don't have the book, but the answer sounds very visual.
Click to expand...
Another question: could you please explain to me why retiming flipflop can remove divider phase noise? Is it because retiming flipflop kind of eliminate the uncertainty brought by divider jitter?
Thank you in advance.
 

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