Why phase is not zero when frequency is equal to 1 ?

[xiongshoufen]

frequency & phase

anyone can explain to me why phase is not zero when frequency is equal to 1 for rail-to-rail simulation

you can check the following waveform .

thank you very much!!!

 

[xiongshoufen]

Re: frequency & phase

the attachment is rail-to-rail schematic

thanks!!

 

[leonwang]

Re: frequency & phase

the gain curve does not look right...

 

[xiongshoufen]

Re: frequency & phase

the gain curve does not look right...

yes , so i want to know why the curve is not right, could you tell me???

thank you very much!!!

 

[okawa]

frequency & phase

your AC analysis is from 1Hz , you can try from 0.01 or lower. the dominant pole of your OP is very low , smaller than 1. u see the gain decrease directly from 130 db.

 

[xiongshoufen]

Re: frequency & phase

your AC analysis is from 1Hz , you can try from 0.01 or lower. the dominant pole of your OP is very low , smaller than 1. u see the gain decrease directly from 130 db.

dear okawa: thank you very much , your analysis is right. the dominant pole of my OP is only 0.2HZ, could you tell me how to increase dominant pole freq? thanks!!

BTW: could you check my ac simulatoin schematic in attached file , thank you

 

[xiongshoufen]

Re: frequency & phase

dear okawa

according to your suggestion, I simulate my OP again, the attached file is BODE plot, could you check it for me, as you say, the dominant pole is only 0.2Hz, thank you !!

 

[okawa]

frequency & phase

well, the dominant pole is at the output node of the first stage. so you should decrease the output impedance of the first stage. so you may try the following methods:1) increase the bias current, 2)decrease the L of the transistors. in ur AC simulation schematic, 10p capacitor maybe is too large for ur op to drive.there is a zero at about 2Mhz, in order to enchance satability , you should add a resistor cascade with the miller capacitor to move this zero to the left plan.

 

[xiongshoufen]

Re: frequency & phase

well, the dominant pole is at the output node of the first stage. so you should decrease the output impedance of the first stage. so you may try the following methods:1) increase the bias current, 2)decrease the L of the transistors. in ur AC simulation schematic, 10p capacitor maybe is too large for ur op to drive.there is a zero at about 2Mhz, in order to enchance satability , you should add a resistor cascade with the miller capacitor to move this zero to the left plan.

dear okawa

do you think that my ac_simulation schematic is suit to ac simulation in above attached file, thanks!!

 

[okawa]

frequency & phase

if u want to simulate the open loop gain of ur opamp ur circuit may be not right. u may add the signal source to ur circuit as the following statements:
vinn inn 0 Vdc
vinp inp 0 Vdc AC Vac
where Vdc is a DC voltage, Vac is an AC voltage amplitude, for instance 1v.
then use .AC statement to perform AC analysis
if you want to simulate the close loop gain, ur circuit is right, but u need add signal to the positive input port as the above statements.
BTW : r u in Fudan?

 

[Vamsi Mocherla]

Re: frequency & phase

I actually think that other than the RHP zero, the circuit seems OK considering the loads he is driving.The try and put lead compensation using a resistor if you want to move the RHP zero into LHP.

SETUP FOR THE SIMULATION:
====================
If you have a problem with the set up, you can use a very large resistor on the feedback path. Actually the idea of using an inductor is that at high frequencies it is an open circuit......I really do not think from the curves, that there is any problem with the circuit......It is only a simple case of the dominant pole being way too dominant.

 

[xiongshoufen]

Re: frequency & phase

I actually think that other than the RHP zero, the circuit seems OK considering the loads he is driving.The try and put lead compensation using a resistor if you want to move the RHP zero into LHP.

SETUP FOR THE SIMULATION:
====================
If you have a problem with the set up, you can use a very large resistor on the feedback path. Actually the idea of using an inductor is that at high frequencies it is an open circuit......I really do not think from the curves, that there is any problem with the circuit......It is only a simple case of the dominant pole being way too dominant.

dear Vamsi Mocherla

could you tell how to modify the circuit, thank you very much!!!!!!!

 

[Vamsi Mocherla]

Re: frequency & phase

Dear xiong,

In your set up I would have put a high resistor of 1G Ohm or even higher than an inductor because an inductor will try and influence the frequency characteristics in the Low frequency range. But the inductor would suffice.

And inside the circuit, why dont you place a resistor(or an active resistor in terms of MOSFET) in series before the MOSFET based capacitor. It will move your RHP zero into the LHP which will improve your phase margin.

 

[ezt]

Re: frequency & phase

Yes I think the zero is a very big problem here and you should do something about it. but if it is possible you should change your opamp. I mean 0.2 Hz is a very very low dominant pole. maybe you could decrease your DC gain (130 dB !!) in order to increase your dominant pole. However I like the idea about decreasing your load capacitor. you know, 10 pF load is not necessary in every applications. in some designs they use class-AB configurations to tolerate this large load.

Regards
EZT