thanks, kennambo. in theory this is well understood, in switched-cap we also simulated with clock, no problems.
I just first time to do transient simulation check with a constant voltage.
yes, it is like a diode connected, it always at saturation region since the gate and drain are connected to VDD, the effective resistance of the NMOS is relatively large since it's at saturation region. there is no DC current path due to its capacitive load, so, in DC sense, the voltage at the cap node will be equal to VDD given infinite time unless the NMOS is completely off.
use resistive load will surely form a resistive divider.