circuit design digital stopwatch tenth thousand
if the latch is mandatory in my design , just like in the case of designing a stop-watch for example .. here the trigger that fires counting has to be independant from the clock .. i guess it can't be a FF .. except if my operating clock's frequency is real high, and the counting would start at the the next clock edge after triggering (where the time here between triggering and the next edge may be in milliseconds or even less) .. here the error would be relatively small ..
BUT .. what if I want the error to be ZERO .. here i have to use a latch ! .. so, would there be any conflict between using latch in my design and the synthesizability .. and JTAG testing ? ..
Is there any other solution to how can one implement the accurate counting of the stop-watch ?